UC Irvine engineers develop wireless chip enabling fiber-optic level speeds

James B. Milliken, President at University of California System
James B. Milliken, President at University of California System
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Electrical engineers at the University of California, Irvine have developed a new wireless transceiver that operates at radio frequencies up to 140 gigahertz. This technology enables data transmission speeds comparable to those of fiber-optic cables and could support future 6G and advanced data protocols.

The team from UC Irvine’s Samueli School of Engineering designed a silicon chip system that combines both digital and analog processing, resulting in a transmitter and receiver capable of processing digital signals more quickly and with higher energy efficiency than existing technologies. Their work is detailed in two papers published this month in the IEEE Journal of Solid-State Circuits.

“We call this technology a ‘wireless fiber patch cord’ because it offers the blistering speed of fiber optics without the physical cables,” said Payam Heydari, director of UC Irvine’s Nanoscale Communication Integrated Circuits Labs and senior author on both papers. “By operating in the F-band – a frequency range well above current 5G standards — we can offer massive bandwidths that will transform how machines, robots and data centers communicate.”

Heydari explained that his team began working on the concept in 2020 after realizing traditional mixed-signal chip architectures would eventually reach performance limits due to their reliance on power-intensive data converters. “We realized that to reach the elusive 100-gigabit-per-second milestone — which is 100 times the speed of current wireless devices – without melting the chip, we had to fundamentally rethink the circuit topology,” he said. “We envisioned novel, all-analog architectures that could overcome the severe power trade-offs plaguing high-speed designs.”

As wireless speeds increase, traditional methods require more power for data processing. “If we stuck to traditional methods, the battery life of next-generation devices would vanish in minutes,” Heydari said. “Our group’s answer is a transceiver that leapfrogs over current limitations by performing complex calculations in the analog domain, rather than the power-hungry digital domain.”

The new transceiver achieves end-to-end operation at 120 gigabits per second—fast enough to transfer multiple 4K movies almost instantly.

Zisong Wang, former UC Irvine doctoral researcher now at Marvell Technology Inc., led one paper describing what they call a “bits-to-antenna” transmitter. He noted: “The Federal Communications Commission and 6G standards bodies are looking at the 100-gigahertz spectrum as the new frontier… But at such speeds, conventional transmitters that create signals using digital-to-analog converters are incredibly complex and power-hungry and face what we call a DAC bottleneck.” Wang added: “It’s like packing a suitcase perfectly before leaving the house rather than trying to organize it while running to the airport.”

Mohammad Oveisi, a UC Irvine doctoral student who co-authored another paper about their “antenna-to-bits” receiver design, explained their method called RF-domain 64QAM allows for efficient signal creation directly in radio-frequency space. This increases energy efficiency by reducing heat output—a key consideration for portable electronics expected to handle large amounts of data.

Youssef Hassan, lead author on one paper and now with Qualcomm, described challenges with traditional receivers: “Traditional receivers struggle to catch such fast data without using massive, energy-draining components called analog-to-digital converters… Moore’s law suggests we can just make transistors smaller to go faster, but at these extreme speeds, we hit a physical wall known as the sampling bottleneck. Digitizing a 120-Gbps signal typically requires massive analog-to-digital converters that burn watts of power, far too much for a smartphone.”

Instead of pushing electronics harder with higher power demands, Hassan said they used hierarchical analog demodulation: “By breaking the signal down hierarchically in the analog domain…we extract the data using a fraction of the power typically required.” The receiver chip uses only about 230 milliwatts thanks to its fabrication using standard semiconductor processes.

Heydari pointed out broader implications beyond consumer devices: “Our innovation eliminates the need for miles of complex copper wiring inside data centers… Data farm operators can do ultrafast wireless links between server racks, saving considerable money on hardware, cooling and power.” He also noted these chips can be produced cost-effectively through routine manufacturing services.

This research was funded by support from programs including Microelectronics Commons under the U.S. Department of Defense.



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